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Design Verification Engineer Soc
Design Verification Engineer SocFondazione Chips-IT • Pavia, IT
Design Verification Engineer Soc

Design Verification Engineer Soc

Fondazione Chips-IT • Pavia, IT
16 giorni fa
Descrizione dell’offerta di lavoro
Experienced Verification Engineer needed for advanced digital IP and SoC development. Responsibilities include creating and maintaining verification environments using UVM, ensuring functional correctness, and collaborating with design teams.
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Design Verification Engineer Soc • Pavia, IT