Staff Analog Mixed-Signal Design Engineer (f/m/div)

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Qualifiche, competenze e l'esperienza necessaria per questo ruolo sono disponibili nella descrizione completa riportata di seguito.

Build the future nobody’s dreamed of yet...

are you ready to rethink the impossible? As a Staff Analog Mixed-Signal Design Engineer in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

Are you in?Your RoleKey responsibilities in your new roleDesign and verify analog circuits for high-speed SerDes sub-blocks, including de-/serializers, current and voltage-mode drivers, Continuous-Time Linear Equalizers (CTLE), and SlicersPerform analog sign-off activities, including EMI, aging, and other reliability checksCollaborate with System Architecture teams to define and refine specifications for analog sub-blocksEvaluate and select optimal architectural solutions to meet the design specificationsPartner with Digital Design teams to ensure effective control and integration of analog blocksWork closely with Analog Physical Design teams to achieve robust layout implementation for high-frequency critical blocksEngage with Verification teams to ensure high-quality, reliable, and silicon-ready designs Your ProfileQualifications and skills to help you succeedA Master’s degree in Electrical/Electronic Engineering or a related field of study5+ years of experience in analog design for high-speed SerDes IpsKnowledge of SerDes sub-block design, including de-/serializers, current and voltage-mode drivers, Continuous-Time Linear Equalizers (CTLE), slicers, and related circuitsExperience with Analog Design Tools (e.g., Virtuoso, Spectre, and others)Experience with FinFET technologies is a strong advantageStrong collaborative mindset with the ability to work effectively in cross-functional teams as well as eagerness to learn and continuously develop technical expertise in advanced analog designFluency in English (mandatory)Please send us your CV in English.Contact: Rita Costa, LinkedIn#WeAreIn for driving decarbonization and digitalization.As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT.

Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals.

Be a part of making life easier, safer and greener.Are you in?We are on a journey to create the best Infineon for everyone.This means we embrace diversity and inclusion and welcome everyone for who they are.

At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities.

We base our recruiting decisions on the applicants experience and skills.

Learn more about our various contact channels.We look forward to receiving your resume, even if you do not entirely meet all the requirements of the job posting.Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.Click here for more information about Diversity & Inclusion at Infineon.Pay InformationIndicative Salary Range:Pavia, Italy43440 -59730The stated salary comprises annual base pay and target variable compensation. xlwpduy

The starting salary is determined using objective, gender neutral criteria, including relevant experience, qualifications, and role scope; prior compensation is not requested or considered.

Employees also benefit from a comprehensive total rewards package, which may include further compensation and benefit elements depending on local regulations and company policieJob Family:Research & DevelopmentType of employment:Duration of employment:PermanentWorkplace type:HybridPreferred start date:Join As:ProfessionalIs this position eligible for Hire4IFX?:YesDepartment:DES DOS IP AMS CM CIS HSIO