Lead of Silicon Design Support Infrastructure

About Fondazione Chips-IT

The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.

The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.

Missions of the Foundation:

• Promote the design and development of integrated circuits
• Strengthen the system of professional training in the field of microelectronics
• Ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field

Fondazione Chips-IT is seeking a Lead of Silicon Design Support Infrastructure to establish and lead the Design, Validation and Test Infrastructure Group. This Group will enable multi-domain semiconductor demonstrator development (Digital, Analog, Power) supporting internal research teams and collaborations with university and industry partners.

The Group will have a central role in the operation of Chips-IT, providing the best possible environment for Research Groups to develop their projects. Its capabilities should bring the Foundation to demonstration levels of TRL 5 to 7 depending on the projects, while also providing infrastructure access for academic and industrial partners within established collaboration frameworks.

The work can be carried out either in Pavia or in Bologna.

KEY RESPONSIBILITIES

Set-Up of the Group

• In coordination with the Research Groups Directors, will define and propose to the CEO the organisation of the Silicon Infrastructure Group and present a 3-year budget forecast
• Together with the HR Manager, will define the profiles of the personnel, engineers and technicians, to recruit (initially between 5 and 10 people)
• It is expected that the infrastructure will provide the following:

1. EDA Tool Management: Installing, maintaining, and upgrading EDA software licenses from vendors like Synopsys, Cadence, Siemens, and Keysight for digital, analog, mixed-signal, and power IC design
2. Computing Infrastructure Optimization: Managing computing environments, including compute clusters, storage, and networking, to support compute-intensive design and simulation workloads across digital, analog, and power domains
3. Workflow Automation: Continuously developing and optimizing multi-domain design workflows from architecture through tape-out, using advanced tools and techniques to enable efficient silicon demonstrator development
4. Advanced Design Tools: Evaluating and enabling cutting-edge design automation tools and methodologies across all semiconductor domains to accelerate development cycles and enhance design quality
5. Emulation and Pre-Silicon Validation: Providing emulation infrastructure for digital designs and supporting hardware-software co-design for demonstrators
6. Multi-Domain Test Facility: Providing comprehensive test capabilities across digital, analog, and power domains including:

• Silicon characterization for digital, analog, and mixed-signal ICs
• Power electronics validation (power analyzers, high-voltage benches, thermal characterization
• RF/analog measurement infrastructure (network/spectrum analyzers, precision equipment)
• Lab automation and safety compliance for all test domains
• Foundry and Fabrication Coordination: Managing foundry relationships, PDK installations, tape-out scheduling, shuttle run organization, and post-silicon debug support across all technology domains

Management of the Group

• Licensing and Compliance: Managing software licensing costs, compliance, and vendor relationships for multi-domain EDA tools
• Data Management & Security: Ensuring security for sensitive design data and managing IP (Intellectual Property) for design reuse across digital, analog, and power projects
• Test Facility Management and Safety: Ensuring that the test facility supports multi-domain silicon validation and demonstration needs (digital, analog, power), optimizing lab utilization and guaranteeing safety standards including high-voltage compliance
• Technical Roadmap Support: Support the Foundation Management in defining technical roadmaps and resource allocation to ensure infrastructure enables multi-domain silicon demonstration objectives from architecture through tape-out and validation
• Methodology Governance: Establish and maintain common design methodologies and best practices across research groups in all semiconductor domains to ensure efficient IP reuse and design optimization
• Collaboration Infrastructure Management: Establishing and managing shared access policies for university and industry partners, including remote access to tools and computing resources, IP protection frameworks, and multi-party project coordination
• Technology Scouting and Assessment: Continuously monitoring emerging technologies, tools, and methodologies across digital, analog, and power domains to identify potential enablers for research projects, evaluating their applicability and coordinating pilot implementations
• Technical Relations with Foundries: Building and maintaining strategic relationships with foundry partners, technology providers to ensure access to cutting-edge processes for all semiconductor domains
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• Proactive Research Support: Support the Research Groups in their multi-domain silicon development projects in a proactive manner, leveraging deep semiconductor experience to ensure common approaches, methodology alignment, and resource optimization

The candidate is a semiconductor sector professional with at least 15 years of industrial experience in R&D or product development and with a broad set of knowledge and skills.

He/She has already managed multi-skilled groups and led development projects in the

pre-production phase and is willing to take the challenge of fully setting up a new activity in a research environment.

In particular, he/she will have:

Technical Expertise

• Knowledge of EDA Infrastructure: Familiarity with tools for RTL design, logic synthesis, analog and RF design, physical design, and simulation. Experience organizing infrastructure for complete design-to-silicon flows across digital, analog, and power domains
• Knowledge of Test Facility Infrastructure: Familiarity with silicon characterization equipment, lab automation, instrumentation for post-silicon validation, safety procedures and compliance requirements
• Power Electronics Infrastructure: Familiarity with test equipment and methodologies specific to power management ICs, DC-DC converters, AC-DC conversion, including high-voltage safety compliance and thermal validation
• Analog/Mixed-Signal Test Capabilities: Understanding of analog and RF characterization requirements, measurement equipment, and validation methodologies for mixed-signal demonstrators
• Silicon Design Flow Understanding: Understanding of ASIC/SoC development from specification through tape-out, including familiarity with foundry processes, PDKs, and design for manufacturability
• Foundry Ecosystem Knowledge: Experience with foundry processes, PDK management, tape-out coordination, and understanding of semiconductor manufacturing

WHAT WE OFFER

• Competitive compensation and contract type, to be negotiated based on qualifications and experience
• Possibility to enter into a PhD conjugating your job with a research program that will grant you the PhD title.
• Lunch tickets
• Private health care coverage depending on your role and contract
• Structured growth path, with ongoing access to training and updates
• Networking opportunities with industry-leading professionals
• International environment
• Hybrid work policy
• Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years
  

In conformità con le normative vigenti, il range retributivo lordo annuo previsto per questa posizione è compreso tra Euro 25.000,00 e 55.000,00. L'ampiezza del range è finalizzata a valutare candidature con diversi livelli di seniority; l'offerta finale sarà strettamente commisurata all'effettiva esperienza e alle competenze del candidato, e sarà integrata dai benefit aziendali previsti per il ruolo.